The present invention relates generally to the field of memory cell arrays and apparatus for checking the integrity of data provided from and/or to such memory cell arrays.
Prior conventional memory cell arrays and their associated cell addressing apparatus typically did not provide any satisfactory way of insuring that the data stored and subsequently read out of such arrays was correct. FIGS. 1 and 2 of the present application indicate a prior memory cell apparatus and the structure of a conventional individual memory cell, respectively. With such previous memory cell array apparatus, the only way to check the integrity of the memory cell array was to essentially duplicate, in a redundant apparatus, all of the memory cell locations and all of the associated row and column decoder circuits, and then provide for reading data into both the primary and redundant array, reading data out of both of these arrays and comparing the output data to insure proper data correspondence. However, this did not detect any errors which might equally effect the data in both of the arrays, such as errors in the row or column address signals which are provided to both of the arrays. Also, such systems would be large and very costly in that they would essentially require the duplication of the memory cell array and its associated address decoder circuitry, as well as requiring additional circuitry to sequentially and/or simultaneously operate and compare both memory cell arrays. Unless a completely duplicate memory cell array and its associated row and column decoder circuitry was provided, prior systems could not detect any failure of a row or column decoder which would result in the addressing of the wrong memory cell and therefore the obtaining of the wrong data from an array.